module HC_FPGA_Demo_Top
(
    input CLOCK_XTAL_50MHz,
	input RESET,
	input  KEY1,
	input  KEY2,
    input  RXD,
    output TXD,
    output LED0,
    output LED1,
    output LED2,
    output LED3,
	 output[7:0] DIG,
	 output[5:0] SEL
);


my_latch u_latch(.A(~KEY1),.B(~KEY2),.C(LED3));




endmodule
